A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving < ?44-dBc HD3 Up To 1.5-V_p-p Output Swing Over 0.01–5.4-GHz for Direct RF Sampling Applications

In this article, we propose a CMOS active balun targeting high linearity up to voltage swing and over wide bandwidth for direct RF sampling applications. All the blocks of are derived using common highly linear building block (HLBB). The HLBB is designed an inverter with strong source degeneration. To increase further, its nonlinearity mechanisms analyzed in detail. A bootstrapping technique included reduce dominant nonlinearity. Furthermore, pre-distortion cancels most non-linearity output driving stages. linearization techniques proposed robust process, voltage, temperature (PVT) changes. measured results realized on-chip 22-nm FDSOI shows $ < -$ 44-dBc third harmonic distortion (HD3) 1.5- notation="LaTeX">$\text{V}_{\textrm {p-p}}$ 0.01–5.4 GHz. gain phase errors action less than 0.5 dB notation="LaTeX">$\pm 5{^\circ }$ , respectively. chip powered from 5-V supply dissipates 925 mW.